The disclosed subject matter relates generally to computer systems and, more particularly, to buffer management using freelist buffers.
In computer systems, devices communicate with one another over buses. The communication efficiency over the bus directly ties into the overall performance of the system. One bus technology used for high speed communication between devices is commonly referred to as HyperTransport (HT). In general, an HT bus is a bidirectional, serial/parallel, high-bandwidth, low-latency, point-to-point link.
In typical HT bus implementations a plurality of virtual channels are defined for communication between devices. Exemplary devices include microprocessors, graphics processors, I/O devices, bridge devices, external caches, network interfaces, cryptoprocessors, etc. Each device maintains a plurality of buffers for communicating across the channel. These buffers are hard-allocated for particular virtual channels. Exemplary channels include a request channel, a response channel, a posted request channel, a probe virtual channel, etc. Multiple virtual channels are provided to avoid deadlocks in the network. For example, without separate virtual channels, the buffers could be allocated to a plurality of request transactions, leaving no buffers available for responses.
For each channel, a number of buffers are hard-allocated for receiving packets of the particular type. The device transmitting the particular packet maintains a count of buffers available for each virtual channel. When a particular packet is sent over the channel, the available buffer count for that channel is decremented by the transmitting device. The receiving device decodes an incoming packet to identify the appropriate virtual channel, and stores the incoming packet in a buffer allocated for the appropriate virtual channel. As the receiving device completes particular requests, thereby freeing up previously used buffers, it sends to the transmitting device a buffer release packet indicating the number of buffers for the various virtual channels that have been released. By maintaining buffer counts for each virtual channel and tracking buffers as they are released, the relative bandwidths of the virtual channels can be controlled.
The performance of the HT bus is affected by the total number of buffers available for communication over the HT bus and the relative buffer counts hard-allocated to each virtual channel. In general, increasing the performance of the HT bus involves allocating more buffers to the various virtual channels. Increasing buffer counts increases the cost of the devices by consuming additional silicon real estate. The number of buffers hard-allocated to each virtual channel is also a performance compromise. The devices communicating over the bus will experience different workloads at different times depending on the particular tasks being performed. The general hard allocation scheme represents an average expected balance between the channels. If a particular task requires different relative uses the virtual channels, the performance of the HT bus may be negatively affected by less efficient usage. There may be a shortage of buffers for one virtual channel, while a different virtual channel experiences a surplus.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.